This invention relates to information processing systems and methods.
Information processing systems can be used for many different applications such as voice recognition, image enhancement or other modification, image recognition, image marking or labelling, image storage and so on. Conventionally, the information is stored in a contiguous block of memory (frame store) and a processor receives signals from each element of that memory for use in the image processing. For a typical image input comprising 512 lines each of 512 pixels and a frame rate of 25 frames/second this gives a data input of 512.times.512.times.25=6,553,600 bytes/second. This input rate may be too high to be processed in real time by software, requiring software processing in less than real time or the need for additional processing capacity.
Multiple processors could be used, with each processor having access to the frame store. The processing speed, however, will be limited by the shared access to the information in the store since only one processor at a time will be able to have access to the information.
In one prior system described in Fung U.S. Pat. No. 4,380,046 there is described a system in which an image is loaded by sending column elements, or pixels, to each of several processors at one end of an array of processors. After processing these pixels, the edge processors pass on the column data to the next adjacent processor and the edge processors read the next column data. Information is therefore, supplied to all but the edge processors via other processors; in the case of the edge processors, their information is output via other processors. This limits the speed of operation of the system and makes it highly sensitive to failure or fault in any one processor. It also limits the flexibility of the system.
In another prior system described by Potter in IEEE Computer, Vol. 16, No. 1, January 1983, a Single Instruction, Multiple Data (SIMD) architecture is employed where all of several processors obey the same instructions at the same time. It is inherent in the design of this system that data cannot be loaded directly into all the processors but must be passed from processor to processor. Again, this limits the flexibility of the system and imposes geometrical constraints on how the data may be allocated to the processors. The system, in effect, acts like a massively parallel single processor in that it obeys only one program.